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| W964B6BBN 1M WORD x 16 BIT LOW POWER PSEUDO SRAM Table of Contents1. GENERAL DESCRIPTION.................................................................................................................. 3 2. FEATURES ......................................................................................................................................... 3 3. PRODUCT OPTIONS ......................................................................................................................... 3 5. Ball DESCRIPTION ............................................................................................................................. 4 6. BLOCK DIAGRAM .............................................................................................................................. 5 7. FUNCTION TRUTH TABLE ................................................................................................................ 6 8. ELECTRICAL CHARACTERISTICS ................................................................................................... 7 Absolute Maximum Ratings .............................................................................................................. 7 Recommended Operation Conditions............................................................................................... 7 Capacitance ...................................................................................................................................... 8 DC Characteristics ............................................................................................................................ 8 AC Characteristics ............................................................................................................................ 9 Read Operation ..........................................................................................................................................9 Write Operation.........................................................................................................................................11 Power Down and Power Down Program Parameters ...............................................................................13 Other Timing Parameters .........................................................................................................................13 AC Test Conditions...................................................................................................................................13 9. TIMING WAVEFORMS ..................................................................................................................... 14 Read Timing #1 ( OE Control Access)............................................................................................ 14 Read Timing #2 ( CE1 Control Access) .......................................................................................... 15 Read Timing #2 ( CE1 Control Access) .......................................................................................... 16 Read Timing #3 (Address Access after OE Control Access) ........................................................ 17 Read Timing #4 (Address Access after CE1 Control Access) ....................................................... 18 Write Timing #1 ( CE1 Control) ....................................................................................................... 19 Write Timing #2-1 ( WE Control, Single Write Operation) .............................................................. 20 Write Timing #2 ( WE Control, Continuous Write Operation) ......................................................... 21 Read/Write Timing #1-1 ( CE1 Control)........................................................................................... 22 Read/Write Timing #1-2 ( CE1 Control)........................................................................................... 23 Publication Release Date: March 31, 2003 Revision A1 -1- W964B6BBN Read ( OE Control) / Write ( WE Control) Timing #2-1 .................................................................. 24 Read ( OE Control) / Write ( WE Control) Timing #2-2 .................................................................. 25 Power Down Program Timing ......................................................................................................... 26 Power Down Entry and Exit Timing................................................................................................. 26 Power-up Timing #1 ........................................................................................................................ 26 Power-up Timing #2 ........................................................................................................................ 27 Standby Entry Timing after Read or Write ...................................................................................... 27 10. PACKAGE DIMENSION.................................................................................................................. 28 TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm)................................................................................ 28 11. ORDERING INFORMATION........................................................................................................... 29 12. VERSION HISTORY ....................................................................................................................... 30 -2- W964B6BBN 1. GENERAL DESCRIPTION W964B6BBN is a 16M bits CMOS pseudo static random access memory (Pseudo SRAM), organized as 1M words x 16 bits. Using advanced single transistor DRAM architecture and 0.175 m process technology; W964B6BBN delivers fast access cycle time and low power consumption. It is suitable for mobile device application such as Cellular Phone and PDA, which high-density buffer is needed and power dissipation is most concerned 2. FEATURES * Asynchronous SRAM interface * Fast access cycle time: * Wide operating conditions: - VDD = +2.3V to +2.7V * Temperature - tRC = 70 nS (-70), 80 nS (-80) * Low power consumption: - TA = 0C to +70C - TA = -25C to +85C (Extended temperature) - TA = -40C to +85C (Industrial temperature) - IDDA1 = 20 mA Max. - IDDS1 = 70 A Max. * Byte write control 3. PRODUCT OPTIONS PARAMETER W964B6BBN70 W964B6BBN80 tRC IDDS1 IDDA1 VDD 70 nS Min. 70 A Max. 20 mA 2.3V to 2.7V 80 nS Min. 70 A Max. 20 mA 2.3V to 2.7V -3- Publication Release Date: March 31, 2003 Revision A1 W964B6BBN 4. BALL CONFIGURATION Top view 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 B DQ9 UB A3 A4 CE1 DQ1 C DQ10 DQ11 A5 A6 DQ2 DQ3 D VSS DQ12 A17 A7 DQ4 VDD E VDD DQ13 NC A16 DQ5 VSS F DQ15 DQ14 A14 A15 DQ6 DQ7 G DQ16 A19 A12 A13 WE DQ8 H A18 A8 A9 A10 A11 NC ( FBGA48 , 6 x 8mm , pitch 0.75mm ) 5. BALL DESCRIPTION SYMBOL DESCRIPTION A0 - A19 CE1 Address input Chip Enable Input 1, Low: Enable Chip Enable Input 2, High: Enable, Low: Enter Power Down mode Write enable input Output Enable input Lower byte write control Upper byte write control Data inputs/outputs Power supply Ground No Connection CE2 WE OE LB UB I/O0 - I/O15 VDD VSS NC -4- W964B6BBN 6. BLOCK DIAGRAM VDD VSS A0 to A18 ADDRESS LATCH & BUFFER MEMORY CELL ARRAY 33,554,432 bits ROW DECODER DQ1 to DQ8 DQ9 to DQ16 INPUT / OUTPUT BUFFER INPUT DATA LATCH & CONTROL SENSE / SWITCH COLUMN / DECODER OUTPUT DATA CONTROL ADDRESS LATCH & BUFFER CE2 PE CE1 WE LB UB OE POWER CONTROL TIMING CONTROL -5- Publication Release Date: March 31, 2003 Revision A1 W964B6BBN 7. FUNCTION TRUTH TABLE Mode Standby (Deselect) Output Disable No Read H Read *2 H L Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down *3 L X X X L H H L L X L H L X Valid Valid Valid X L L *4 Valid Note CE2 CE1 WE OE LB X X H UB X X H A0-18 X *5 Valid DQ1-8 High-Z High-Z High-Z Output Valid Invalid Input Valid Input Valid High-Z DQ9-16 High-Z High-Z High-Z Output Valid Input Valid Invalid Input Valid High-Z IDD IDDS Data Retention Yes H *1 X H X H IDDA Yes IDDP No/Yes Notes: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High impedance, KEY = Key Address. *1: Output Disable mode should not be kept longer than 1 S. *2: Byte control at Read mode is not supported. *3: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IDDP current and data retention depend on the selection of Power Down Program. *4: Either or both LB and UB must be Low for Read operation. *5: Can be either VIL or VIH but must be valid before Read or Write. -6- W964B6BBN 8. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PARAMETER SYMBOL VALUE UNIT Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Storage Temperature VDD VIN, VOUT IOUT TSTG -0.5 to +3.6 -0.5 to +3.6 50 -55 to +125 V V mA C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Recommended Operation Conditions (Reference to VSS) PARAMETER NOTES SYMBOL MIN. MAX. UNIT Supply Voltage High Level Input Voltage Low Level Input Voltage Ambient Temperature Ambient Temperature Ambient Temperature Notes: VDD VSS *1 *2 VIH VIL TA TA TA 2.3 0 2.0 -0.3 0 -25 -40 2.7 0 VDD +0.3 0.4 70 85 85 V V V V C C C *1: Maximum DC voltage on input and I/O pins are VDD +0.3V. During voltage transitions, inputs may positive overshoot to VDD +1.0V for periods of up to 5 nS. *2: Minimum DC voltage on input and I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot to 1.0V for periods of up to 5 nS. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users considering application outside the listed conditions are advised to contact their Winbond representative beforehand. -7- Publication Release Date: March 31, 2003 Revision A1 W964B6BBN Capacitance Test conditions: TA = 25C, f = 1.0 MHz SYMBOL DESCRIPTION TEST SETUP TYP. MAX. UNIT CIN1 CIN2 CIO Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance VIN = 0V VIN = 0V VIO = 0V - 5 5 8 pF pF pF DC Characteristics (Under Recommended Operating Conditions unless otherwise noted) PARAMETER SYM. TEST CONDITIONS notes*1, *2, *3 MIN. MAX. UNIT Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level (TTL) Standby Current (CMOS) ILI ILO VOH VOL IDDS VIN = VSS to VDD VOUT = VSS to VDD, Output Disable VDD = VDD, IOH = -0.5 mA IOL = 1 mA VDD = VDD Max., VIN = VIH or VIL CE1 = CE2 = VIH VDD = VDD Max., VIN 0.2V or VIN VDD -0.2V, CE1 = CE2 VDD -0.2V -1.0 -1.0 1.8 - +1.0 +1.0 0.4 3 A A V V mA IDDS1 - 70 A mA mA IDDA1 Active Current IDDA2 Notes: VDD = VDD Max., VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = Minimum tRC / tWC = 1 S - 20 3 *1: All voltages are reference to VSS. *2: DC Characteristics are measured after following POWER-UP timing. *3: IOUT depends on the output load conditions. -8- W964B6BBN AC Characteristics (Under Recommended Operating Conditions unless otherwise noted) Read Operation PARAMETER SYM. -70 Min. Max. Min. -80 Max. UNIT NOTES Read Cycle Time Chip Enable Access Time Output Enable Access Time Address Access Time Output Data Hold Time CE1 Low to Output Low-Z tRC tCE tOE tAA tOH tCLZ tOLZ tCHZ tOHZ tASC tASO tASO[ABS] tBSC tBSO tAX tCLAH tOLAH tCHAH tOHAH tCHBH tOHBH tCLOL tOLCH tCP tOP tOP[ABS] 70 5 5 0 -5 30 10 -5 10 70 40 -5 -5 -5 -5 25 35 12 25 12 65 40 65 20 20 5 1000 1000 - 80 5 5 0 -5 35 10 -5 10 80 45 -5 -5 -5 -5 30 40 15 30 15 75 45 75 25 25 5 1000 1000 - nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS ns *5, *7, *8 *6 *3, *5, *7, *8 *7 *9 *1, *3 *1 *1 *1 *2 *2 *2 *2 *4 *3, *5 *6 OE Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z Address Setup Time to CE1 Low Address Setup Time to OE Low LB / UB Setup Time to CE1 Low LB / UB Setup Time to OE Low Address Invalid Time Address Hold Time from CE1 Low Address Hold Time from OE Low Address Hold Time from CE1 High Address Hold Time from OE High LB / UB Hold Time from CE1 High LB / UB Hold Time from OE High CE1 Low to OE Low Delay Time OE Low to CE1 High Delay Time CE1 High Pulse Width OE High Pulse Width -9- Publication Release Date: March 31, 2003 Revision A1 W964B6BBN Read Operation, Continued Notes: *1: The output load is 30 pF. *2: The output load is 5 pF. *3: The tCE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4: Applicable if OE is brought to Low before CE1 goes Low. *5: The tASO, tCLOL(min.) and tOP(min.) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO(actual), is shorter than specified minimum value, tASO(min), during OE control access (ie., CE1 stays Low), the tOE become tOE(max.) + tASO(min.) - tASO(actual). *6: The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. *7: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC(min.) tCLOL(actual) or tRC(min.) - tOP(actual). *8: Maximum value is applicable if CE1 is kept at low. - 10 - W964B6BBN AC Characteristics, Continued Write Operation PARAMETER SYM. -70 Min. Max. Min. -80 Max. UNIT NOTES Write Cycle Time Address Setup Time Address Hold Time CE1 Write Setup Time CE1 Write Hold Time tWC tAS tAH tCS tCH tWS tWH tBS tBH tOES tOEH tOEH[ABS] tOHCL tOHAH tCW TWP tWRC tWR tDS tDH tCP 70 0 35 0 0 0 0 -5 -5 0 30 12 -5 -5 45 45 10 10 15 0 12 1000 1000 1000 1000 1000 - 80 0 40 0 0 0 0 -5 -5 0 35 15 -5 -5 50 50 15 15 20 0 15 1000 1000 1000 1000 1000 - nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS *1 *2 *2 WE Setup Time WE Hold Time LB and UB Setup Time LB and UB Hold Time OE Setup Time OE Hold Time OE High to CE1 Low Setup Time OE High to Address Hold Time CE1 Write Pulse Width *3 *3, *4 *5 *6 *7 *1, *8 *1, *8 *1, *9 *1, *3, *9 WE Write Pulse Width CE1 Write Recovery Time WE Write Recovery Time Data Setup Time Data Hold Time CE1 High Pulse Width *9 - 11 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN Write Operation, Continued Notes: *1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR). *2: New write address is valid from either CE1 or WE is brought to High. *3: The tOEH is specified from end of tWC(min.). The tOEH(min.) is a reference value when the access time is determined by tOE. If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. *4: The tOEH(max.) is applicable if CE1 is kept at Low and both WE and OE are kept at High. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low. *6: tOHCL(min.) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL(min.), WE Low must be asserted after tRC(min.) from CE1 Low. In other words, read operation is initiated if tOHCL(min.) is not satisfied. *7: Applicable if CE1 stays Low after read operation. *8: tCW and tWP is applicable if write operation is initiated by CE1 and WE , respectively. *9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE , respectively. The tWR(min.) can be ignored if CE1 is brought to High together or after WE is brought to High. In such case, the tCP(min.) must be satisfied. - 12 - W964B6BBN AC Characteristics, Continued Power Down and Power Down Program Parameters PARAMETER SYM. -70 Min. Max. -80 Min. Max. UNIT NOTES CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1 High Setup Time following CE2 High after Power Down Exit tCSP tC2LP tCHS 10 70 10 - 10 80 10 - nS nS nS Other Timing Parameters PARAMETER SYM. -70 Min. Max. -80 Min. Max. UNIT NOTES CE1 High to OE Invalid Time for Standby Entry CE1 High to WE Invalid Time for Standby Entry tCHOX tCHWX tC2LH tC2HL tCHH tT 10 10 50 50 350 1 25 10 10 50 50 350 1 25 nS nS S S S nS *1 *2 *3 *2 *4 CE2 Low Hold Time after Power-up CE2 High Hold Time after Power-up CE1 High Hold Time following CE2 High after Power-up Input Transition Time Notes: *1: Some data might be written into any address location if tCHWX(min.) is not satisfied. *2: Must satisfy tCHH(min.) after tC2LH(min.). *3: Requires Power Down mode entry and exit after tC2HL. *4: The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5 nS, it may violate AC specified of some timing parameters. AC Test Conditions SYMBOL DESCRIPTION TEST SETUP VALUE UNIT NOTE VIH VIL VREF TT Input High Level Input Low Level Input Timing Measurement Level Input Transition Time VDD = 2.3V to 2.7V VDD = 2.3V to 2.7V VDD = 2.3V to 2.7V Between VIL and VIH 2.0 0.4 1.1 5 V V V nS - 13 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN 9. TIMING WAVEFORMS Read Timing #1 ( OE Control Access) tRC tRC ADDRESS ADDRESS VALID tCE tOHAH ADDRESS VALID tASO tOHAH CE1 tOLCH tCLOL OE tOE tOP tOE tASO tBSO tOHBH tBSO tOHBH LB / UB tOLZ DQ (Output) tOHZ tOH tOLZ tOHZ tOH VALID DATA OUTPUT VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 14 - W964B6BBN Timing Waveforms, Continued Read Timing #2 ( CE1 Control Access) tRC tRC ADDRESS tASC CE1 ADDRESS VALID tCE tCHAH tASC ADDRESS VALID tCE tCHAH tCP OE tBSC LB / UB tOLZ DQ (Output) tCHZ tOH tCLZ tCHZ tOH tCHBH tBSC tCHBH VALID DATA OUTPUT VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 15 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN Timing Waveforms, Continued Read Timing #2 ( CE1 Control Access) tRC tRC ADDRESS tASC CE1 ADDRESS VALID tCE tCHAH tASC ADDRESS VALID tCE tCHAH tCP OE tBSC LB / UB tOLZ DQ (Output) tCHZ tOH tCLZ tCHZ tOH tCHBH tBSC tCHBH VALID DATA OUTPUT VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 16 - W964B6BBN Timing Waveforms, Continued Read Timing #3 (Address Access after OE Control Access) tRC ADDRESS tASO CE1 tOE OE tBSO LB / UB tOLZ DQ (Output) VALID DATA OUTPUT tOH ADDRESS VALID tOLAH tAX tRC ADDRESS VALID tAA tOHAH tOHZ tOHBH tOH VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 17 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN Timing Waveforms, Continued Read Timing #4 (Address Access after CE1 Control Access) tRC ADDRESS tASC CE1 tCE OE tBSC LB / UB tCLZ DQ (Output) VALID DATA OUTPUT tOH ADDRESS VALID tCLAH tAX tRC ADDRESS VALID tAA tCHAH tCHZ tCHBH tOH VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 18 - W964B6BBN Timing Waveforms, Continued Write Timing #1 ( CE1 Control) tWC ADDRESS tAS CE1 tWS WE tBS LB / UB tOHCL OE tDS DQ (Intput) VALID DATA INTPUT tDH tBH tBS tWC tWH tWRC tWS ADDRESS VALID tAH tAS Note: CE2 and PE must be High for entire write cycle. - 19 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN Timing Waveforms, Continued Write Timing #2-1 ( WE Control, Single Write Operation) tWC ADDRESS tOHAH CE1 tOHCL WE tBH LB / UB tOES OE tOHZ DQ (Intput) VALID DATA INTPUT tDS tDH tBS tBH tCS tWP tWR tAS ADDRESS VALID tAH tCH tAS tCP Note: CE2 and PE must be High for entire write cycle. - 20 - W964B6BBN Timing Waveforms, Continued Write Timing #2 ( WE Control, Continuous Write Operation) tWC ADDRESS tOHAH CE1 tOHCL WE tOHBH LB / UB tOES OE tOHZ DQ (Intput) VALID DATA INTPUT tDS tDH tBS tBH tBS tCS tWP tWR tAS ADDRESS VALID tAH tAS Note: CE2 and PE must be High for entire write cycle. - 21 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN Timing Waveforms, Continued Read/Write Timing #1-1 ( CE1 Control) tWC ADDRESS tCHAH CE1 tCP tWH WE tCHBH LB / UB tOHCL OE tCHZ tOH DQ (Intput) VALID DATA INTPUT VALID DATA INTPUT tDS tDH tOLZ tBS tBH tBSO tWS tCW tWH tWRC tWS tCLOL tAS ADDRESS VALID tAH tAS Note: Write address is valid from either CE1 or WE of last falling edge. - 22 - W964B6BBN Timing Waveforms, Continued Read/Write Timing #1-2 ( CE1 Control) tRC ADDRESS tWRC CE1 tASC ADDRESS VALID tCHAH tCP tWH WRITE ADDRESS tAS tWRC(min) tWH tWS tWS tBS WE tBH LB / UB tOEH OE tCHZ tDH DQ tCLZ tOH tBSC tOE tCHBH tOHCL VALID DATA OUTPUT VALID DATA OUTPUT Note: The tOEH is specified from the time satisfied both tWRC and tWR(min). - 23 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN Timing Waveforms, Continued Read ( OE Control) / Write ( WE Control) Timing #2-1 tWC ADDRESS tOHAH CE1 Low tWP WE tOHBH LB / UB tOES OE tOHZ tOH DQ (Intput) VALID DATA INTPUT VALID DATA INTPUT tDS tDH tOLZ tBS tBH tOEH tWR tOEH tAS WRITE ADDRESS tAH READ ADDRESS tASO Note: CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE . - 24 - W964B6BBN Timing Waveforms, Continued Read ( OE Control) / Write ( WE Control) Timing #2-2 tRC ADDRESS tASO CE1 Low tWR WE tBH LB / UB tOE OE tOHZ tDH DQ tOLZ tOH tBSO tOHBH tBS tOEH ADDRESS VALID tOHAH WRITE ADDRESS tAS tOES VALID DATA OUTPUT VALID DATA OUTPUT Note: CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE . - 25 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN Timing Waveforms, Continued Power Down Program Timing CE1 tEPS tEP tEPH PE tEAS ADDRESS (A20-16) KEY tEAH Note: CE2 must be High for Power Down Program operation. Any other inputs not specified above can be either High or Low. Power Down Entry and Exit Timing CE1 tCHS CE2 tCSP tC2LP High-Z Power Down Entry Power Down Mode Power Down Exit tCHH (tCHHN) DQ Note: This Power Down mode can be also used for Power-up #2 below except that tCHHN can not be used at Power-up timing. Power-up Timing #1 CE1 tCHS tC2LH CE2 tCHH VDD 0V VDD min Note: The tC2LH specifies after VDD reaches specified minimum level. Timing Waveforms, Continued - 26 - W964B6BBN Power-up Timing #2 CE1 tC2HL CE2 tC2HL tCSP tC2LP tCHS tCHH VDD 0V VDD min Note: The tC2HL specifies from CE2 low to High transition after VDD reaches specified minimum level. CE1 must be brought to High prior to or together with CE2 Low to High transition. Standby Entry Timing after Read or Write CE1 tCHOX OE tCHWX WE Active (Read) Standby Active (Write) Standby Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC(min) period from either last address transition of A0, A1 and A2, or CE1 Low to High transition. - 27 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN 10. PACKAGE DIMENSION TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm) - 28 - W964B6BBN 11. ORDERING INFORMATION PART NO. SPEED OPERATING TEMPERATURE PACKAGE W964B6BBN70 W964B6BBN70E W964B6BBN70I W964B6BBN80 W964B6BBN80E W964B6BBN80I Notes: 70 nS 70 nS 70 nS 80 nS 80 nS 80 nS 0 to 70 -25 to 85 -40 to 85 0 to 70 -25 to 85 -40 to 85 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 29 - Publication Release Date: March 31, 2003 Revision A1 W964B6BBN 12. VERSION HISTORY VERSION DATE PAGE DESCRIPTION A1 March 31, 2003 - Create new document Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 30 - |
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